As integrated circuit (IC) process technology has scaled, it has become increasingly difficult to control the variation of transistor parameters. Because of such random variations, threshold voltage variations become a limiting factor in transistor design as process technology is scaled downward because voltage cannot be similarly scaled. In particular, threshold voltage variations between neighboring metal-oxide-semiconductor field effect transistors (MOSFETs) can have significant impact on the area and performance characteristics of dynamic random access memory (DRAM) devices. For example, threshold voltage variations between the cross-coupled p-channel MOS (PMOS) and/or n-channel MOS (NMOS) transistors in a typical DRAM sense amplifier can lead to increased data signal voltages on the bit lines to compensate for these variations. Other DRAM peripheral circuits can also be affected by the threshold voltage variations.
One way of reducing variation, improving performance, and decreasing overall power requirement relies on selective body bias control of transistors. However, there are many considerations to consider for best body bias operation in DRAM devices. Application of any particular body bias is typically inappropriate, since different circuits benefit from different biases, which may change with the mode of operation. For instance, some circuits benefit from higher performance, with leakage being of relatively less importance (e.g., sense amplifiers), while leakage is critical in others (e.g., data buffers). Additionally, some circuits may be excessively sensitive to noise produced on reverse-body biased transistors. For example, charge pump generated biases are known to negatively impact delay line performance, with the noise introducing a substantial jitter. This is due, in part, to the required reverse body bias (RBB) voltages typically being beyond the power supply levels (i.e., rails) of the device. Working around this limitation is difficult, since adding other power supplies can be prohibited by relevant industry standards, and in any case would substantially increase required circuit layout area and the bill of materials due to extra pins and power supplies. Moreover, since the charge pumps cannot supply RBB voltages immediately upon IC power-up (by definition they must pump sufficient charge into the required power rails first) devices using RBB may have excessive transistor leakage during power-up and power-on reset.